This application claims the benefit of Korean Patent Application No. 2001-68395, filed on Nov. 3, 2001, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
This invention relates to an electro-luminescence display (ELD), and more particularly to an electro-luminescence panel that is adaptive for maximizing a capacitance of a storage capacitor.
2. Discussion of the Related Art
Recently, various flat panel display devices have been developed reduced in weight and bulk that are capable of eliminating the disadvantages of a cathode ray tube (CRT). Such flat panel display devices include a liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and electro-luminescence (EL) panels, etc.
Studies have been done for increasing a display quality of the flat panel display device and for providing the flat panel display with a large-scale screen. The EL panel in such display devices is a self-emission device. The EL panel excites a fluorescent material using carriers such as electrons and holes, etc. to display a video image. The EL panel has advantages in that a low direct current voltage driving is possible and a response speed is fast.
As shown in FIG. 1, such an EL panel includes gate lines GL1 to GLm and data lines DL1 to DLn arranged on a glass substrate 10 in such a manner to cross each other, and pixel elements PE arranged at crossings between the gate lines GL1 to GLm and the data lines DL1 to DLn. Each of the pixel elements PE is driven when gate signals on the gate lines GL1 to GLm are enabled, thereby generating light corresponding to the magnitude of a pixel signal on the data line DL.
In order to drive such an EL panel, a gate driver 12 is connected to the gate lines GL1 to GLm while a data driver 14 is connected to the data lines DL1 to DLn. The gate driver 12 sequentially drives the gate lines GL1 to GLm. The data driver 14 applies pixel signals, via the data lines DL1 to DLn, to the pixel elements PE.
As shown in FIG. 2, each of the pixel elements PE driven with the gate driver 12 and the data driver 14 consists of an EL cell OELD connected to a ground voltage line GND, and a cell driving circuit 16 for driving the EL cell OLED.
FIG. 2 is a detailed circuit diagram of the pixel element PE shown in FIG. 1, which includes a driving circuit arranged at a crossing between the gate line GL and the data line DL that is comprised of two TFTs T1 and T2.
Referring to FIG. 2, the pixel element PE includes an EL cell OLED connected to a ground voltage source GND, and an EL cell driving circuit 16 connected between the EL cell OLED and the data line DL.
The EL cell driving circuit 16 includes the second NMOS TFT T2 connected between the EL cell OLED and the supply voltage line VDD to serve a driver, a first NMOS TFT T1 connected between the data line DL and the gate electrode of the second NMOS TFT T2 to serve a switch of the EL cell OLED, and a storage capacitor Cst connected between the drain electrodes of the first NMOS TFT T1 and the supply voltage line VDD.
In this case, when a gate voltage is changed from a turn-on voltage Von into a turn-off voltage Voff upon formation of the storage capacitor Cst regarding the supply voltage line VDD as an opposite electrode, a capacitance value (Q=CV) is reduced to thereby cause a kickback phenomenon in which a data voltage having a level slightly lower than a normal level is applied. Also, because it is required to have ground voltage source GND and additional lines for increasing the capacitance, an aperture ratio and the stability of the process are reduced.
FIG. 3 is a detailed circuit diagram of another example of the pixel element PE shown in FIG. 1, which includes a driving circuit arranged at a crossing between the gate line GL and the data line DL that is comprised of two TFTs T1 and T2.
Referring to FIG. 3, the pixel element PE includes an EL cell OLED connected to a ground voltage source GND, and an EL cell driving circuit 26 connected between the EL cell OLED and the data line DL.
The EL cell driving circuit 26 includes the second NMOS TFT T2 connected between the EL cell OLED and the supply voltage line VDD to serve a driver, the first NMOS TFT T1 connected between the data line DL and the gate electrode of the second NMOS TFT T2 to serve a switch of the EL cell OLED, and a storage capacitor Cst connected between the drain electrodes of the first NMOS TFT T1 and the ground voltage line GND or a common voltage line.
In this case, since such an inclusion of the common voltage line for compensating for a kickback effect in the storage capacitor Cst requires a separate line, a problem arises in that an aperture ratio is reduced and a stability of a process for providing the voltage line is deteriorated.
Accordingly, the present invention is directed to an electro-luminescence panel that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
It is an advantage of the present invention to provide an electro-luminescence panel wherein a capacitance value of a storage capacitor is maximized with the aid of the pre-stage gate line upon formation of the storage capacitor, thereby reducing a kickback effect.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the method particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, VCS embodied and broadly described, an electro-luminescence panel according to an embodiment of the present invention includes a plurality of gate lines; a plurality of data lines crossing the gate lines; a plurality of electro-luminescence cells arranged at crossings between the gate lines and the data lines; and an electro-luminescence cell driving circuit for driving the electro-luminescence cells, said electro-luminescence cell driving circuit including a power supply for supplying power to the electro-luminescence cells; a first thin film transistor connected between the power supply and the electro-luminescence cell; a second thin film transistor connected between the data line and a gate electrode of the first thin film transistor to serve a switch of the electro-luminescence cell; and a first capacitor connected between the gate electrode of the first thin film transistor and a pre-stage gate line.
The electro-luminescence panel the further includes second capacitor connected between the gate electrode of the first thin film transistor and the power supply.
In the electro-luminescence panel, the first thin film transistor and the second thin film transistor are any one type of PMOS type or NMOS type.
An electro-luminescence panel according to embodiment of the present invention includes a gate lines and data lines arranged on a glass substrate to cross each other; pixel elements arranged at crossings between the gate lines and data lines; each of the pixel elements driven when gate signals on the gate lines are enabled, wherein light corresponding to the magnitude of a pixel signal on the data line is generated; a gate driver connected to the gate lines, wherein the gate driver sequentially drives the gate lines; and a data driver connected to the data lines, wherein the data driver applies pixel signals, via the data lines, to the pixel elements.
In the electro-luminescence panel, each of the pixel elements consists of an electro-luminescence cell connected to a ground voltage source and an electro-luminescence cell driving circuit for driving the electro-luminescence cell.
In the electro-luminescence panel, the electro-luminescence driving circuit includes a second PMOS TFT connected between the electro-luminescence cell and a supply voltage line to serve a driver, a first PMOS TFT connected between a data line and the gate electrode of the second PMOS TFT to serve as a switch of the electro-luminescence cell, and a storage capacitor connected between the drain electrodes of the first PMOS TFT and a pre-stage gate line.
In the electro-luminescence panel, the electro-luminescence driving circuit includes a second NMOS TFT connected between the electro-luminescence cell and a supply voltage line to serve a driver, a first NMOS TFT connected between a data line and the gate electrode of the second NMOS TFT to serve as a switch of the electro-luminescence cell, and a storage capacitor connected between the drain electrodes of the first NMOS TFT and a pre-stage gate line.
In the electro-luminescence panel, the electro-luminescence driving circuit includes a second PMOS TFT connected between the electro-luminescence cell and a supply voltage line to serve a driver, a first PMOS TFT connected between a data line and the gate electrode of the second PMOS TFT to serve as a switch of the electro-luminescence cell, a first storage capacitor connected between the drain electrodes of the first PMOS TFT and a pre-stage gate line; and a second storage capacitor connected between the drain electrode of the first PMOS TFT and the supply voltage line.
In the electro-luminescence panel, the electro-luminescence driving circuit includes a second NMOS TFT connected between the electro-luminescence cell and a supply voltage line to serve a driver, a first NMOS TFT connected between a data line and the gate electrode of the second NMOS TFT to serve as a switch of the electro-luminescence cell, a first storage capacitor connected between the drain electrodes of the first NMOS TFT and a pre-stage gate line; and a second storage capacitor connected between the drain electrode of the first NMOS TFT and the supply voltage line.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the intention as claimed.